Bonding Properties of Package-on-Package Stack Interconnection Using by 150 ㎛ Height Copper Posts

Mi-Song Kim; So-Hee Hyun; Joo Young Bae; Won Sik Hong

doi:10.5781/JWJ.2024.42.4.5

Abstract

In this study, we used copper (Cu) posts, plated to a height of 150 μm, as interconnections to form electrodes between different package layers. The upper layer consisted of a chip-scale package (CSP), while the lower layer was made up of a flip chip-chip scale package (FCCSP). We plated a Cu post on the side of FCCSP substrate, and produced the FCCSP package by thermo-compression (TC) bonding with copper pillar solder bumps on the center of substrate. The surface of the bottom electrode for the upper CSP received a surface finish of electroless nickel, electroless palladium, and immersion gold (ENEPIG). The bonding surface of the lower FCCSP was the bare Cu surface of the epoxy-molded Cu post. The PoP joining process used a vacuum reflow process with solder paste and solder balls. To understand the package joint’s characteristics, we measured voids and shear strength, and analyzed the cross-sectional microstructure. The temperature profile used in the PoP joining process demonstrated optimal joint characteristics with a joint void content of 2.3% and a joint strength of approximately 44 MPa when formic acid was utilized and the activation preheating time was extended. Cross-sectional warpage analysis of the PoP package revealed a minimal difference of approximately 31 μm between the center and the ends. This study successfully developed a stacked package with a PoP structure using Cu Post, and the bonding process was optimized to minimize warpage in the PoP package.

Key words: Pakcage-on-package (PoP), Vacuum reflow, Cu post, Multilayer ceramic capacitor (MLCC), Cu pillar solder bump, Warpage

1. Introduction

With the advancement of electronic devices and artificial intelligence technology, the demand for highly integrated semiconductor packages is increasing. Intercon- nection technologies for semiconductor packages include bonding wire and flip chip bonding techniques. The bonding wire technique connects the top of the chip to the substrate using metallic wires but has the disadvantage of not being able to use the entire chip surface due to the issue of wire shorts. On the other hand, the flip chip bonding technique directly connects the bottom of the chip to the substrate using solder bumps, allowing the entire chip surface to be used for interconnections and enabling faster signal processing, making it more suitable for highly integrated semiconductor packages¹^-⁹⁾. However, even this highly integrated bonding technology has limitations in the number of signals that can be handled by a single chip or package area, necessitating stacking technology to process additional signals.

Stacking technologies for semiconductor packages include chip stacking techniques that stack chips via flip chip bonding or wire bonding, through silicon via (TSV) technology that creates through holes in silicon chips and fills them with electrode material, and package stacking technologies such as package-on-package (PoP) and package-in-package (PiP), which stack flip- chip chip-scale packages (FCCSP) or chip-scale packages (CSP). Chip stacking technology enables the implementation of smaller packages, but it has the drawback that if even one internal chip is defective after the stacking process, the entire package must be discarded. On the other hand, package stacking technology results in larger packages but allows for the stacking of packages with various functions and the replacement of defective packages with new ones after stacking.

A representative package stacking technology is the package-on-package (PoP) technique, where, as shown in Fig. 1(a), solder balls are applied to the periphery of the lower FCCSP to bond it with the upper CSP. The size of the solder balls must be larger than the height of the chip inside the FCCSP, and since the bonding involves the substrate surface of the FCCSP, epoxy molding compound (EMC) cannot be applied. Warpage that occurs during the bonding process is due to the difference in the coefficient of thermal expansion (CTE) of the package components. The CTEs of Si chips and substrates are 2.6 and 15 ppm/°C, respectively, and warpage can be adjusted by molding the package with EMC, which has a CTE of 12 ppm/°C. As shown in Fig. 1(a), the upper CSP and lower FCCSP have different structure, and according to previous studies, the warpage of the upper CSP and lower FCCSP during the bonding process appears as convex or concave shapes, respectively¹⁰⁾. This warpage shape difference between the upper and lower packages can cause defects in the PoP stacking bonding process, making it important to properly control the package structure and warpage.

Fig. 1

Cross-sectional schematic diagram of (a) commercial and (b) developed PoP stack structures

Surface finishes for package electrode pads include organic solderability preservative (OSP), electroless- nickel immersion-gold (ENIG), and electroless-nickel electroless-palladium immersion-gold (ENEPIG). OSP joints tend to form many voids due to relatively high oxidation, while the ENEPIG surface prevents the occurrence of black pads seen on ENIG surfaces and suppresses the formation of Kirkendall voids at the joints, thus providing excellent mechanical reliability¹¹^-¹⁸⁾.

In this study, a PoP package stacking bonding technology was developed to interconnect an upper CSP with ENEPIG finish to a lower FCCSP using copper posts with a height of 150 ㎛ (Fig. 1(b)). In the developed PoP structure, EMC can be applied to both the upper and lower packages, resulting in the same warpage shape, and eliminating the need for solder balls larger than the chip height, thereby allowing for the transmission of more signals. Solder balls and solder paste composed of Sn-3.0Ag-0.5Cu (SAC305) were used, and after optimizing the PoP bonding process, shear strength and cross-sectional microstructure were analyzed. In addition, to apply multilayer ceramic capacitors (MLCCs) to the PoP package, substrates for MLCC bonding were fabricated with the same thickness and material, and the bonding characteristics of MLCCs were evaluated according to the bonding process.

2. Experimental Methods

2.1 Raw Material Analysis

The substrate of the lower FCCSP used two types of bismaleimide triazine (BT) substrates with different Cu post arrays, as shown in Fig. 2 (a) and (b). The substrates measured 12×12 mm with a thickness of 0.3 mm. The ENEPIG surface treatment thicknesses were Ni 3-8 ㎛, Pd 0.05-0.15 ㎛, and Au 0.05-0.15 ㎛. As presented in Fig. 2 (c), the Cu posts were visually confirmed to be well-formed, and cross-sectional analysis was conducted to verify the plating thickness of the Cu posts.

Fig. 2

Optical images of BT substrates plated with (a) 400 and (b-c) 800 pitch Cu posts, and (d) Si chip for FCCSP

The Si chip for flip-chip bonding (Fig. 2(d)) and the internal structure of the lower substrate (Fig. 2 (a,b)) were designed in a daisy chain pattern to facilitate flip-chip bonding. The electrical connection status was verified by measuring the resistance of the Cu pillar solder bump joints at different segments. Inside the Si chip, Cu pillar solder bumps with a diameter of 60 ㎛ and a pitch of 100 ㎛ were formed, and their microstructure was analyzed through cross-sectional analysis.

2.2 MLCC and Flip Chip Bonding

To optimize the bonding process for MLCCs, an MLCC bonding substrate was fabricated as shown in Fig. 3 (d), and the bonding characteristics were compared by MLCC size. Using a metal mask with 100% aperture and 50 ㎛ thickness, Type 7 (2-11 ㎛) Sn-3.0Ag- 0.5Cu (SAC305) solder paste was printed. MLCCs of sizes C0402, C0603, C1005, C1608, and C2012 (mm) were then soldered to the chip. The bonding process applied hot air type, nitrogen type, and vacuum type reflow processes, with the respective temperature profiles shown in Fig. 3 (a-c). The flip chip bonding process for the lower FCCSP utilized a thermo-compression bonding process, with the process profile presented in Fig. 4. After bonding, the void content and shear strength of each joint were analyzed to determine the optimal bonding conditions. The void content analysis involved measuring the area of the joints and the void areas to calculate the percentage of the total void area.

Fig. 3

Bonding profiles of (a) hot air type reflow, (b) nitrogen type reflow, (c) vacuum type reflow and (d) optical image of MLCC substrate

Fig. 4

(a) Temperature profile of flip chip bonding and (b) optical image after flip chip and BT substrate interconnect

2.3 Optimization of PoP Bonding Process

For PoP bonding, the lower FCCSP underwent flip chip bonding and EMC molding, followed by mechanical grinding of the package’s top surface to expose the Cu post surfaces, as shown in Fig. 5(b). The upper CSP of the PoP package, shown in Fig. 5(a), had SAC305 solder balls with a diameter of 250 ㎛ arranged on the bottom surface, and the PoP bonding process with the lower FCCSP was optimized.

Fig. 5

Optical images of (a) bottom side of CSP and (b) top side of FCCSP

The jig used for the PoP bonding process is shown in Fig. 6. Since the Cu post surface of the lower FCCSP was in a bare Cu state after grinding without any surface treatment, an ethanol cleaning and oxide removal process was performed before the PoP bonding process. The oxide removal process utilized vacuum type reflow equipment, with the profile set to the activation temperature range of formic acid, as shown in Fig. 7(a), injecting formic acid along with nitrogen. Subsequently, the upper CSP was bonded to the Cu post surface using the process profiles depicted in Fig. 6(b-d), and the bonding characteristics were compared through void content, bonding strength, and cross-sectional analysis. The process temperature profiles in Fig. 7(b-c) show the profiles with and without formic acid injection during the process, while Fig. 7(c-d) compares the bonding process characteristics based on the temperature setting conditions of the preheating temperature range (150- 180 °C) of formic acid.

Fig. 6

Optical photograpshs of (a) guide jigs and (b) inside the jig for PoP bonding process

Fig. 7

Temperatrue profiles of (a) oxide layer removal process, (a) reflow without formic acid, (c) reflow with formic acid, and (d) the preheating section with a slop for PoP bonding

3. Experiment Results

3.1 Raw Material Analysis

The cross-sectional analysis results of the lower FCCSP substrate are shown in Fig. 8 (a-d). Uniformly thick Cu posts, each exceeding 150 ㎛, were arranged. For substrate 2, due to the smaller total plating area, the Cu posts were thicker compared to substrate 1. The cross-sectional analysis of the Si chip for flip chip bonding, as depicted in Fig. 8 (e-f), confirmed that the Cu pillar Sn-2.5Ag solder bumps were well-formed.

Fig. 8

Cross-sectional SEM micrographs of (a,c) substrate 1, (b,d) substate 2 and (e-f) Si chip for FCCSP

3.2 Characteristics of MLCC and Flip Chip Joints

The analysis results of MLCC joint voids and bonding strength for various processes are shown in Fig. 9. For C2012 MLCCs, the bonding strength was highest in the vacuum type, followed by nitrogen and hot air types. For C1608 MLCCs, the bonding strength was similar across all types. For MLCCs sized C1005 and smaller, the bonding strength was comparable in hot air and vacuum types, and the lowest in the nitrogen type. The void content in MLCC joints was the lowest in the vacuum type. For C2012 and C1608 MLCCs, the void content was lower in the nitrogen type than in the hot air type, but for MLCCs sized C1005 and smaller, the void content tended to increase. This increase in the void content seemed to cause the reduced bonding strength in the nitrogen type. Despite expectations that the void content would be lower in the nitrogen type than in the hot air type due to oxidation effects in the bonding processes using Type 7 solder paste, the opposite result was observed for MLCCs sized C1005 and smaller. It appears that the solvent in the solder paste is volatilized due to the nitrogen injected to reduce the oxygen concentration, and the fluidity of the voids is reduced, thereby increasing the void content in the solder joint. Especially in MLCC joints smaller than C1005, the amount of solder paste is smaller. The decrease in solder paste leads to an overall decrease in absolute amount of solvents and activators, allowing the process environment to have greater influence.

Fig. 9

Shear Strength and void content by MLCC size and various processes

After the flip chip bonding process for the lower FCCSP, as shown in Fig. 10, the void content across all segments was approximately 1.7%, and the bonding strength was measured to be about 34 MPa.

Fig. 10

X-ray non-destructive analysis images after thermal compression bonding of flip chip and BT substrate

3.3 Characteristics of MLCC and Flip Chip Joints

Fig. 11 demonstrates the cross-sectional micrographs of PoP joints with and without the oxide removal process. Without the oxide removal process, the solder was non-wetting on the Cu post, as shown in Fig. 11(a). After applying the pre-treatment process for oxide removal, a stable bonding state was formed, as shown in Fig. 11(b). The highest void content according to the PoP bonding process profile was observed to be 7.1% when formic acid was not injected, as shown in Fig. 12(a). When formic acid was injected and the activation temperature range was maintained, as shown in Fig. 12(b), the void content was the lowest at 2.3%, and the shear strength of the PoP joint was approximately 44 MPa.

Fig. 11

Cross-sectional micrographs of PoP solder joints (a) without and (b) with oxide layer removal process

The cross-sectional warpage of the PoP package was measured as shown in Fig. 13. Fig. 13(a) illustrates the gap difference between the center and the edge of the package due to warpage. The gap differences due to warpage were 31 ㎛ for substrate 1, which had more densely bonded solder balls, and 21 ㎛ for substrate 2, indicating minimal warpage. The cross-sectional analysis of the PoP joint, as shown in Fig. 14, confirmed stable bonding between the upper CSP and lower FCCSP. The upper part of the PoP joint revealed the formation of (Cu,Ni,Au)₆Sn₅ intermetallic compound (IMC), while the lower part showed the formation of Cu₆Sn₅ IMC. In the flip chip joints, (Cu, Ni,Au)₆Sn₅ IMC was formed in both the upper and lower parts.

Fig. 12

X-ray non-destructive analysis (a-c) images and (d) void content after PoP bonding

Fig. 13

(a) Schematic diagram and (b-e) results of cross-sectional warpage analysis after PoP bonding: (b,d) substrate 1 type, (c,e) substrate 2 type

Fig. 14

Cross-sectional (a,b,c,e) SEM micrographs and (d,f) EDS analysis results after PoP bonding of (a,c,d) solder ball joint, (b) PoP joint in the center of the package and (e,f) Cu pillar solder joint

4. Conclusion

This study developed a PoP stacking technology by applying a substrate with Cu post plating to the lower FCCSP, and optimized the MLCC, flip chip, and PoP bonding processes.

1) Hot air, nitrogen, and vacuum type reflow processes were applied, and bonding characteristics were evaluated by process type and MLCC type. The vacuum type reflow process had the best bonding characteristics, with a void content of 0.4% for C2012 MLCC and bonding strength of 4.8 kgf.
2) The most outstanding bonding characteristics, with a void content of 2.3% at the joint and bonding strength of 44 MPa, were achieved when formic acid was used for the PoP temperature profile and the preheating time was extended. Cross-sectional warpage analysis of the PoP package showed a difference of about 31 ㎛ between the center and the edge, indicating minimal warpage after the PoP stacking bonding process. The stacked package with a PoP structure was successfully developed using Cu posts, and the bonding process was optimized to minimize warpage in the PoP package.