Recent Progress of TGV Technology for High Performance Semiconductor Packaging

Seok, Beom Chang; Jung, Jae Pil

doi:2024.42.2.155

J Weld Join > Volume 42(2); 2024 > Article

Research Paper

Journal of Welding and Joining 2024;42(2):155-164.
DOI: https://doi.org/10.5781/JWJ.2024.42.2.2 Published online April 30, 2024.

Recent Progress of TGV Technology for High Performance Semiconductor Packaging

Beom Chang Seok

, Jae Pil Jung

Dept. of Materials Science and Engineering, University of Seoul, Seoul, 02504, Korea

Correspondence: Jae Pil Jung,
Email: jpjung@uos.ac.kr

Received: 7 March 2024 • Revised: 14 March 2024 • Accepted: 27 March 2024

Abstract

In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.

Key Words: Through glass via, Semiconductor, Electronics packaging, Cu filling